1. Field of the Invention
The present invention relates to a digital phase-locked loop (DPLL) for use in stuffing synchronization, and more particularly to a fully secondary DPLL for use in a synchronous digital hierarchy (SDH).
2. Description of the Prior Art
SDH employs pointer operation which uses byte stuffing, and generates eight [UI/time] phase gaps in one control period. PLLs for use in SDH are required to have a very narrow frequency band in order to suppress phase gaps that are generated by pointer operation, i.e., insertion and removal of stuffing pulses.
A Bit-Leaking method is known as a scheme for achieving a PLL having a very narrow frequency band. According to the Bit-Leaking method, eight [UI/time] phase gaps generated by pointer operation are divided into 1 [UI] units and scattered (bit-leaked) at certain time intervals for thereby reducing jitter amplitudes. The Bit-Leaking method is a digital version of the phase-locked loop (PLL) that has traditionally been used in the art. FIG. 1 of the accompanying drawing shows the Bit-Leaking method.
As shown in FIG. 1, an input signal 20 and an output signal 30 are compared in phase with each other by a phase comparator 40, which applies an output signal to a low-pass filter 50. The low-pass filter 50 smoothes the output signal from the phase comparator 40, and supplies an output signal to a variable-control oscillator 60, which produces an output signal 30 depending on the output signal from the low-pass filter 50. According to a Fixed Bit-Leaking scheme, the phase comparator 40 has positive and negative thresholds, and the phase gaps are bit-leaked at fixed periods if the phase error or difference between write and read clock signals exceeds the thresholds. According to an Adaptive Bit-Leaking scheme, the phase gaps are bit-leaked depending on a phase error that is detected by the phase comparator 40.
The Fixed Bit-Leaking scheme is disadvantageous in that control is not uniform, posing limitations on the suppression of jitter, because the control period is constant regardless of the number of times the pointer is controlled per second, and hence control pulses are concentrated in the constant period. In the Adaptive Bit-Leaking scheme, to uniformize control quantities in the time domain, a steady phase error corresponding to the amount by which the pointer is controlled is generated for controlling the variable-control oscillator. Therefore, a buffer memory provided at the former stage of the PLL needs to be large enough to absorb the steady phase error that is generated. In addition, since it is necessary to increase the time constant of the system for keeping a strong jitter suppression capability, the period of time that is consumed to bring the system into operation is long in proportion to the amount by which the pointer is controlled.